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| CXD2401R Electronic Iris Control IC Description The CXD2401R is an IC which performs electronic iris control by applying a CCD electronic shutter. Features * Electronic iris control drive * Generates system clocks in response to the CXA1390AR series * Generates timing pulses to drive the 510H system CCD image sensor * H driver for CCD (5V direct drive for 1/2" and 1/3" CCD) Absolute Maximum Ratings * Supply voltage VDD VSS - 0.5 to +7.0 V * Input voltage VI VSS - 0.5 to VDD + 0.5V * Output voltage VO VSS - 0.5 to VDD + 0.5V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -55 to +150 C Recommended Operating Conditions * Supply voltage VDD 4.75 to 5.25 * Operating temperature Topr -20 to +75 VDD3 GM 48 pin LQFP (Plastic) Applications CCD monitoring cameras Structure Silicon gate CMOS IC Applicable CCD Image Sensors 510H system SONY CCD * ICX054AK (1/3" NTSC CCD) * ICX055AK (1/3" PAL CCD) * ICX026CKA (1/2" NTSC CCD) * ICX027CKA (1/2" PAL CCD) V C VSS3 XSUB XSG2 XV4 XV3 36 VSS4 SPUPV IRIN SPDNV Vreg VDD4 ENB IRENB PS LIMIT1 LIMIT2 NTSC 37 38 39 40 41 42 35 34 33 32 31 30 29 28 27 26 25 24 XV2 23 22 XDL2 XDL1 XV1 RG H2 H1 Pin Configuration XSG1 21 XSP2 20 19 CXD2401R 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 XSP1 XSHP VSS2 XSHD VDD2 CLP2 BFG ID 43 44 45 46 47 48 OSCI OSCO VDD1 CLP4 CLP1 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. TEST -1- PBLK VD VSS1 HD CK CL E94620C6X-PS CXD2401R Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol OSCI OSCO CK TEST CL VSS1 VD HD VDD1 CLP4 CLP1 PBLK ID BFG CLP2 VDD2 XSHD VSS2 XSHP XSP1 XSP2 XDL1 XDL2 XV2 XV1 XSG1 XV3 XSG2 XV4 XSUB VSS3 H1 H2 RG I/O I O I I O -- I I -- O O O O O O -- O -- O O O O O O O O O O O O -- O O O Description Inverter input for oscillation. (NTSC: 1820fH, PAL: 1816fH) Inverter output for oscillation. (NTSC: 1820fH, PAL: 1816fH) Input for main clock in IC. (NTSC: 1820fH, PAL: 1816fH) IC test input. Fixed at GND in normal operation. (With pull-down resistor) CK/2 clock output. NTSC: 910fH = 4fsc, PAL: 908fH GND Vertical sync signal input. Horizontal sync signal input. 5V power supply. Clamping pulse for CCD dummy output. Clamping pulse for CCD optical black. Cleaning pulse for vertical/horizontal blanking. Vertical direction line identification signal. Burst flag gate pulse. Clamping pulse in horizontal blanking. 5V power supply. CCD data level sample-and-hold pulse output. GND CCD precharge level sample-and-hold pulse output. Color separation sample-and-hold pulse output. Color separation sample-and-hold pulse output. Clock output for CCD DL (Delay Line). Clock output for CCD DL (Delay Line). CCD vertical clock output. CCD vertical clock output. Clock output for CCD sensor readout. CCD vertical clock output. Clock output for CCD sensor readout. CCD vertical clock output. Clock output for CCD electronic shutter. GND CCD horizontal clock output. CCD horizontal clock output. CCD reset gate pulse output. -2- CXD2401R Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Symbol VDD3 GM VSS4 SPUPV IRIN SPDNV Vreg VDD4 ENB IRENB PS LIMIT1 LIMIT2 NTSC I/O -- I -- I I I -- -- I I I I I I 5V power supply. Used for GND connection. GND Description When set in electronic iris mode: Shutter speedup reference voltage input When set in serial mode of electronic shutter: Strobe input When set in electronic iris mode: Iris signal input When set in serial mode of electronic shutter: Clock input When set in electronic iris mode: Shutter speed-down reference voltage input When set in serial mode of electronic shutter: Data input Current source for comparator. Connected to 5V power supply via 33k resistor. 5V power supply. Generation/halt switching of electronic shutter pulse (Pin 30). (With pull-up resistor) Electronic iris/electronic shutter switching. (With pull-up resistor) Parallel/serial input switching of electronic shutter speed data. (With pull-up resistor) Selecting limit value of max. shutter speed. (With pull-down resistor) Selecting limit value of max. shutter speed. (With pull-down resistor) NTSC/PAL switching. (With pull-down resistor) Electrical Characteristics DC Characteristics Item Pin No. Symbol VDD Conditions (Within recommended operating range) Min. 4.75 1.9 VSS 0.7VDD 0.3VDD IOH = -4mA IOL = 8mA IOH = -8mA IOL = 8mA IOH = -20mA IOL = 20mA IOH = -2mA IOL = 4mA VIL = 0V VIH = VDD 25 25 50 50 VDD - 0.8 0.4 75 75 VDD - 0.8 0.4 VDD - 0.8 0.4 VDD - 0.8 0.4 Typ. 5.0 Max. 5.25 VDD VDD Unit V V V V V V V V V V V V V k k Supply voltage 1 9, 16, 35, 42 Input voltage 1 Input voltage 2 Input voltage 3 38, 40 (Electronic iris mode) VIN1 39 (Electronic iris mode) 4, 7, 8, 36, 38, 39, 40, 43, 44, 45, 46, 47, 48 (Pins 38, 39 and 40 are when set in electronic shutter mode) VIN2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOH4 VOL4 RPU RPD Output voltage 1 5, 10, 11 15, 17, 19, 20, 21, 22, 23, 34 Output voltage 2 Output voltage 3 32, 33 12, 13, 14, 24, 25, 26, 27, 28, 29, 30 43, 44, 45 4, 36, 46, 47, 48 Output voltage 4 Pull-up resistance value Pull-down resistance value Pins 7 and 8 do not have a protective diode at the power supply side. -3- CXD2401R Comparator Characteristics Item Input offset voltage Response Rise time Fall Current consumption In-phase input voltage range Indefinite region Pin No. Symbol Vos Conditions (Within recommended operating range) Min. Typ. 1.1 Response time when a step input of 100mV amplitude/ 5mV overdrive is applied. 140 190 98 1.9 to 5 10 140 Max. 50 Unit mV ns ns A V mW 38, 39, 40 tpd + tpd - IDD VICR Vf Bias current source for comparator. Pin No.: 41. Connected to power supply via 33k resistor. Note) 1. Input offset voltage and indefinite region Input offset voltage and indefintie region are existed in the comparator which builds in this IC as shown right figure. Note that this when designing external circuit. 2. Pins 40 and 38 for electronic iris mode Use it in this state of Pin 40 (SPDNV) > Pin 38 (SPUPV). 5.0V Indefinite region 10mV 10mV Pins 40 and 38 (SPDNV and SPUPV) 10mV 10mV Indefinite region GND 50mV 50mV Input offset voltage Input offset voltage Oscillating Inverter I/O Characteristics Item Logical Vth 1 Input voltage Pin No. Symbol LVth VIH VIL 2 1 to 2 VOH VOL RFE f IOH = -12mA IOL = 12mA VIN = VDD or Vss Conditions (Within recommended operating range) Min. Typ. VDD/2 0.7VDD 0.3VDD VDD/2 VDD/2 250k 20 1M 2.5M 30 Max. Unit V V V V V MHz Output voltage Feedback resistor Oscillator frequency Duty Control Inverter Input Characteristics Item Logical Vth Input voltage 3 Input amplification Feedback resistor Pin No. Symbol LVth VIH VIL VIN RFE Conditions (Within recommended operating range) Min. Typ. VDD/2 0.7VDD 0.3VDD fmax = 50MHz sine wave VIN = VDD or Vss 0.5 250k 1M 2.5M Max. Unit V V V Vpp Note) The input voltage is the input voltage characteristics for an external direct power input, and input amplification is the input amplification characteristics for input through capacitor. -4- CXD2401R Electrical Characteristics AC Characteristics 1) AC characteristics among serial communication clocks (SPDNV (ED2), IRIN (ED1), SPUPV (ED0)) SPDNV (ED2) IRIN (ED1) 0.3VDD 0.7VDD 0.7VDD 0.7VDD ts2 SPUPV (ED0) th2 0.3VDD tw0 0.7VDD ts1 ts0 (Within recommended operating range) Symbol Definition SPDNV (ED2) set-up time, activated by the rising edge of IRIN (ED1) SPDNV (ED2) hold time, activated by the rising edge of IRIN (ED1) IRIN (ED1) rising set-up time, activated by the rising edge of SPUPV (ED0) SPUPV (ED0) pulse width SPUPV (ED0) rising set-up time, activated by the rising edge of IRIN (ED1) Min. 20ns 20ns 20ns 20ns 20ns 50s Typ. Max. ts2 th2 ts1 tw0 ts0 2) Microcomputer communication clock IC take-in characteristics Example: NTSC/ODD field VD HD XSG1 Magnification HD XSG1 NTSC mode: 63.5s, PAL mode: 63.9s SEN logic level is to be High for this period. 0.3VDD 0.3VDD Note) During the 1H period for generating XSG1, the phase against AVD differs according to each mode. Please always maintain the SEN logic level at High for "the 1H period when XSG1 varies." -5- CXD2401R 3) HD/VD take-in characteristics HD VD 0.3VDD 0.7VDD 0.3VDD CL ts4 th4 (Within recommended operating range, Load capacity of CL = 30pF) Symbol Definition HD/VD set-up time, activated by CL HD/VD hold time, activated by CL Min. 5 7 Typ. Max. Unit ns ns ts4 th4 4) Phase discrimination characteristics by VD/HD input NTSC: ODD field PAL: EVEN field NTSC: EVEN field PAL: ODD field VD 0.3VDD tpd2 VD 0.3VDD tpd2 HD When the HD logic level is Low tpd2 after VD falls, the phase is discriminated as an ODD field (NTSC). HD When the HD logic level is High tpd2 after VD falls, the phase is discriminated as an EVEN field (NTSC). (Within recommended operating range) Symbol tpd2 Definition Field discriminating clock phase, activated by the falling edge of VD Min. 700 Typ. Max. 1000 Unit ns -6- CXD2401R 5) Phase characteristics of H1, RG, XSHP, XSHD, XSP1, XSP2, XDL1, XDL2, and CL tCK CK Vpp/2 tpd3 H1 tpd5 0.3VDD tpd4 tpd6 0.7VDD RG 0.3VDD tpd8 0.7VDD XSHP tpd7 0.3VDD 0.7VDD tpd9 tpd10 0.7VDD XSHD XSP1 XSP2 XDL1 tpd11 tpd12 0.7VDD 0.3VDD tpd13 tpd16 0.3VDD 0.3VDD tpd15 0.7VDD tpd14 0.7VDD 0.3VDD tpd17 tpd20 0.7VDD tpd18 0.3VDD XDL2 CL tpd19 0.3VDD 0.7VDD (Within recommended operating range) CK-duty = within 50 4%, Load capacity of H1 = 150pF, Load capacity of CL = 30pF, Load capacity of RG, XSHP, XSHD, XSP1, XSP2, XDL1, and XDL2 = 10pF Symbol Definition CK cycle H1 falling delay, activated by the falling edge of CK H1 rising delay, activated by the rising edge of CK RG falling delay, activated by the falling edge of CK RG rising delay, activated by the rising edge of CK XSHP falling delay, activated by the rising edge of CK XSHP rising delay, activated by the falling edge of CK XSHD falling delay, activated by the falling edge of CK XSHD rising delay, activated by the rising edge of CK XSP1 falling delay, activated by the rising edge of CK XSP1 rising delay, activated by the rising edge of CK XSP2 falling delay, activated by the rising edge of CK XSP2 rising delay, activated by the rising edge of CK XDL1 rising delay, activated by the rising edge of CK XDL1 falling delay, activated by the falling edge of CK XDL2 rising delay, activated by the rising edge of CK XDL2 falling delay, activated by the falling edge of CK CL falling delay, activated by the falling edge of CK CL rising delay, activated by the falling edge of CK -7- 16.22 17.25 20.18 18.61 15.86 15.76 14.92 14.76 14.79 15.05 15.09 15.29 14.49 15.05 14.46 14.92 15.33 14.71 Min. Typ. 35 29 31 36 33 28 28 27 26 26 27 27 27 26 27 26 27 27 26 56.9 60.38 70.58 65.32 55.59 55.32 52.26 51.62 51.74 52.58 52.82 53.54 50.79 52.67 50.65 52.47 53.01 51.58 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCK tpd3 tpd4 tpd5 tpd6 tpd7 tpd8 tpd9 tpd10 tpd11 tpd12 tpd13 tpd14 tpd15 tpd16 tpd17 tpd18 tpd19 tpd20 CXD2401R 6) Waveform characteristics of H1 and RG 0.9VDD H1 0.1VDD trH1 tfH1 0.9VDD RG 0.1VDD trRG tfRG VDD = 5.0V, Topr = 25C, Load capacity of H1 = 150pF, Load capacity of RG = 10pF Symbol Definition H1 rise time H1 fall time RG rise time RG fall time Min. Typ. 7 7 3 3 Max. Unit ns ns ns ns trH1 tfH1 trRG tfRG I/O Pin Capacitances Item Input pin capacitance Output pin capacitance I/O pin capacitance Symbol CIN COUT CI/O Min. Typ. Max. 9 11 11 Unit pF pF pF -8- CXD2401R Description of Operation The operations of the CXD2401R are described below. Control pin Detailed description Low: The CXD2401R performs control drive in accordance with NTSC. In this case, the CXD2401R operates by assuming the signals input to Pin 7 (VD) and Pin 8 (HD) are NTSC sync signals. High: The CXD2401R performs control drive in accordance with PAL. In this case, the CXD2401R operates by assuming the signals input to Pin 7 (VD) and Pin 8 (HD) are PAL sync signals. Refer to the "Timing Chart" for the control drive pulse for either NTSC or PAL. Low: Pin 30 (XSUB) is always High. That is, the electronic iris and electronic shutter to which XSUB pulses are applied suspend operation (electronic iris and electronic shutter OFF). High: Pin 30 (XSUB) outputs control pulses for the electronic iris and electronic shutter. (electronic iris and electronic shutter ON). Low: Realizes the electronic shutter control. High: Realizes the electronic iris control. The control pins (SPUPV, IRIN, and SPDNV) are used in common for both electronic shutter control and electronic iris control. The operations of these pins differ depending on the state of IRENB pin. This pin is valid when the operation of electronic shutter is assigned (IRENB = Low). Low: Electronic shutter speed can be controlled by inputting serial data into SPUPV, IRIN, and SPDNV pins. High: Electronic shutter speed can be controlled by inputting parallel data into SPUPV, IRIN, and SPDNV pins. Note) The PS pin is invalid when IRENB = High, and the CXD2401R does not accept data, whether PS is Low or High. NTSC (Pin 48) ENB (Pin 43) IRENB (Pin 44) PS (Pin 45) -9- CXD2401R Control pin Detailed description The operations of SPUPV, IRIN, and SPDNV pins differ according to the mode (IRENB control) of the electronic iris and electronic shutter. The operations are described below for each case. IRENB = Low: When the operation of electronic shutter is assigned PS = Low: When inputting serial data is assigned SPUPV : Strobe input pin IRIN : Clock input pin SPDNV : Data input pin D0 SPUPV (Pin 38) IRIN (Pin 39) SPDNV (Pin 40) SPDNV (ED2) IRIN (ED1) SPUPV (ED0) D7 D6 D5 D4 D3 D2 D1 MSB D7 Ld : Shutter speed data Ex.: Ld = 100 [decimal] 0 D6 1 D5 1 D4 0 D3 0 D2 1 D1 0 LSB D0 0 150 to 114 [875 - {(150 - Ld) x 11 + 253}] x 0.978 + 0.047 196 to 146 145 to 109 108 to 102 101 to 93 92 to 81 80 to 64 63 to 0 - 10 - CXD2401R Control pin Detailed description IRENB = Low: When the operation of electronic shutter is assigned PS = High: When inputting parallel data is assigned Shutter Speed Compatibility Chart SPUPV H L H L H L H L IRIN H H L L H H L L SPDNV H H H H L L L L Shutter speed (s) NTSC(Pin 48) = L NTSC(Pin 48) = H 1/100 1/250 1/500 1/1000 1/2000 1/5000 1/10000 1/100000 1/120 1/250 1/500 1/1000 1/2000 1/5000 1/10000 1/110000 SPUPV (Pin 38) IRIN (Pin 39) SPDNV (40Pin) IRENB = High: When the operation of electronic iris is assigned CXD2401R SPDNV IRIN Comp2 SPUPV Comp1 Shutter Speed Cont DECODE Comp 1 Truth Table SPDNV L H IRIN H L Comp1 H L DECODE Truth Table Comp1 L L H Comp2 L H H Comp2 L H L H Shutter Speed Cont Shutter speed; Faster Shutter speed; Hold Shutter speed; Hold Shutter speed; Slower Comp 2 Truth Table IRIN L H SPUPV H L In the electronic iris control operation, the electronic shutter speed is controlled according to the logic above. The variations of shutter speed by each control are the same as those shown in - 11 - CXD2401R Control pin Detailed description LIMIT1 and LIMIT2 pins function only when IRENB = High (when the operation of electronic iris is assigned). (Inputs from LIMIT1 and LIMIT2 are not accepted when IRENB = Low: when the operation of electronic shutter is assigned.) Maximum Electronic Shutter Speed LIMIT1 LIMIT2 L H L H Max. shutter speed (s) NTSC (Pin 48) = L NTSC (Pin 48) = H 1/200 1/2000 1/20000 1/90000 1/200 1/2000 1/20000 1/100000 Purpose Reduces flickers caused by an indoor fluorescent lamp. Intermediate mode between indoor and outdoor applications. Reduces CCD smear outdoors. Secures dynamic range of iris. LIMIT1 (Pin 46) LIMIT2 (Pin 47) L L H H Electronic iris control of the CXD2401R is realized by applying functions of the electronic shutter. The electronic shutter has a dynamic range from 1/60s when Pin 48 (NTSC) = Low or from 1/50s when Pin 48 (NTSC) = High up to the maximum shutter speed in the table above. Select one of the four dynamic ranges of the electronic iris, according to the application conditions of the CXD2401R. The dynamic range is also determined by also taking into consideration the influence of the electronic shutter on image quality, as shown in the table above. - 12 - NTSC Vertical Direction Timing Chart FLD BLK/VD HD XSG1 XSG2 ID XV1 XV2 - 13 - 490 492 2 46 13 57 491 XV3 XV4 2 468 1357 492 CCD 491 PBLK CLP1 CLP2 CLP4 BFG CXD2401R PAL Vertical Direction Timing Chart FLD BLK/VD HD XSG1 XSG2 ID XV1 - 14 - 582 2468 13579 XV2 XV3 XV4 2 4 6 8 10 13 579 582 CCD 581 PBLK CLP1 CLP2 CLP4 BFG CXD2401R NTSC Horizontal Direction Timing Chart (63) HD BLK 102 BLK/HD CL H1 RG XSHP XSHD XSP1 XSP2 XDL1 XDL2 27 39 21 51 33 50 18 24 75 18 64 56 94 89 94 63 67 94 57 45 - 15 - XV1 XV2 XV3 XV4 XSUB CLP1 2 CLP2 8 CLP4 PBLK ID BFG CXD2401R PAL Horizontal Direction Timing Chart (64) HD 112 BLK BLK/HD CL H1 RG XSHP XSHD XSP1 XSP2 XDL1 50 44 26 56 38 68 55 18 24 80 23 69 61 103 94 103 72 103 62 XDL2 32 - 16 - XV1 XV2 XV3 XV4 XSUB CLP1 2 CLP2 8 CLP4 PBLK ID BFG CXD2401R Readout Timing Chart 1 2 3 4 289 290 [285] [286] Numerals in brackets are for PAL. 1 clock: 104.76ns (NTSC) 105.73ns (PAL) H1 HD XV1 FIELD ODD XV2 XV3 3 24 24 19 XV4 - 17 - 10 14 XV1 XV2 EVEN XV3 XV4 XSG1 XSG2 Unit: Number of clocks (common to NTSC and PAL) CXD2401R NTSC High-speed Phase Timing Chart HD Reset phase Start of H1 and H2 CK 1 93 2 3 112 CL H1 H2 RG - 18 - XSHP XSHD XSP1 XSP2 XDL1 XDL2 CXD2401R PAL High-speed Phase Timing Chart HD Rset phase Start of H1 and H2 CK 1 2 3 100 118 CL H1 H2 RG - 19 - XSHP XSHD XSP1 XSP2 XDL1 XDL2 CXD2401R CXD2401R Application Circuit ICX055AK ICX054AK ICX027CK ICX026CK IRIS GC = 4.1V IRIS LEVEL = 3.0V DET LEVEL = 5.0V CXL1518N CCD CXA1390AQ/AR CXA1391R/Q CXA1392R/Q CXD1267N XDL1 XSHD XSP1 XSHP XSP2 CLP1 PBLK CLP4 H1 H2 RG 30P OSCI OSCO Timing Generator 27P 1000P WND CXD1159Q CK CL VD HD SUBTRACTION SELECTOR D SELECTOR IRENB IRIS/SHUTTER CK GEN CK COUNTER ENB XSUB GATE CXD2401R DECODE UP/DOWN ADDER ED2 ED1 ED0 BFG XV2, XV3, XV4 XSG1, XSG2 CLP2 XDL2 3.9K XV1 ID PS NTSC VSS4 VSS3 VSS2 VSS1 DECODE 6.8K 3.9K 33/16V LIMIT1 LIMIT2 IRIN 33K Vreg GM VDD1 VDD2 VDD3 VDD4 2.3V 2.2K SPUPV SPDNV 2.8V Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 20 - CXD2401R Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 0.2 36 37 7.0 0.1 25 24 (8.0) A 48 1 0.5 0.08 + 0.08 0.18 - 0.03 0.1 0.1 + 0.2 1.5 - 0.1 12 13 (0.22) + 0.05 0.127 - 0.02 0.1 0 to 10 0.5 0.2 NOTE: Dimension "" does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g - 21 - 0.5 0.2 |
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